Tekninen dokumentti
Tekniset tiedot
Merkki
Skyworks Solutions IncMaximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Alkuperämaa
Taiwan, Province Of China
Tuotetiedot
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.
Varastotiedot eivät ole tilapäisesti saatavilla.
Tarkista myöhemmin uudelleen.
€ 42,80
kpl (toimitus tarjottimella) (ilman ALV)
€ 53,07
kpl (toimitus tarjottimella) (Sis ALV:n)
1
€ 42,80
kpl (toimitus tarjottimella) (ilman ALV)
€ 53,07
kpl (toimitus tarjottimella) (Sis ALV:n)
1
Osta irtotavarana
Määrä | Yksikköhinta |
---|---|
1 - 4 | € 42,80 |
5 - 9 | € 39,40 |
10 - 24 | € 38,40 |
25+ | € 37,50 |
Tekninen dokumentti
Tekniset tiedot
Merkki
Skyworks Solutions IncMaximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Alkuperämaa
Taiwan, Province Of China
Tuotetiedot
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.