Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
AND
Mounting Type
Surface Mount
Number Of Elements
4
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
TSSOP
Pin Count
14
Logic Family
LV
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-12mA
Maximum Propagation Delay Time @ Maximum CL
12.3 ns @ 3.3 V, 17.3 ns @ 2.5 V, 7.9 ns @ 5 V
Minimum Operating Supply Voltage
2 V
Maximum Low Level Output Current
12mA
Height
1.15mm
Dimensions
5 x 4.4 x 1.15mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+85 °C
Length
5mm
Width
4.4mm
Minimum Operating Temperature
-40 °C
Product details
74LV Family, Texas Instruments
Low-Voltage CMOS logic
Operating Voltage: 2 to 5.5
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LV Family
€ 13.95
€ 0.279 Each (Supplied on a Reel) (Exc. Vat)
€ 17.51
€ 0.35 Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
50
€ 13.95
€ 0.279 Each (Supplied on a Reel) (Exc. Vat)
€ 17.51
€ 0.35 Each (Supplied on a Reel) (inc. VAT)
Stock information temporarily unavailable.
Production pack (Reel)
50
Stock information temporarily unavailable.
| Quantity | Unit price | Per Reel |
|---|---|---|
| 50 - 190 | € 0.279 | € 2.79 |
| 200 - 490 | € 0.249 | € 2.49 |
| 500+ | € 0.214 | € 2.14 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
AND
Mounting Type
Surface Mount
Number Of Elements
4
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
TSSOP
Pin Count
14
Logic Family
LV
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-12mA
Maximum Propagation Delay Time @ Maximum CL
12.3 ns @ 3.3 V, 17.3 ns @ 2.5 V, 7.9 ns @ 5 V
Minimum Operating Supply Voltage
2 V
Maximum Low Level Output Current
12mA
Height
1.15mm
Dimensions
5 x 4.4 x 1.15mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+85 °C
Length
5mm
Width
4.4mm
Minimum Operating Temperature
-40 °C
Product details
74LV Family, Texas Instruments
Low-Voltage CMOS logic
Operating Voltage: 2 to 5.5
Compatibility: Input LVTTL/TTL, Output LVCMOS


