Renesas Electronics FIFO Memory, 28-Pin PDIP, 7201LA12TPG

The Renesas Electronics FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a retransmit capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

• Pin and functionally compatible with 720X family
• Low power consumption
• Ultra high speed 12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Auto-retransmit capability