Technical Documents
Specifications
Brand
STMicroelectronicsProduct Type
Microprocessor
Series
STM32MP23xA/D
Device Core
ARM Cortex A35, ARM Cortex M33
Data Bus Width
16bit
Instruction Set Architecture
64 Bit, ARM V8-M, Arm Cortex
Maximum Clock Frequency
1.5GHz
Interface Type
SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet
Minimum Supply Voltage
1.71V
Package Type
TFBGA361
Maximum Supply Voltage
3.6V
Pin Count
361
Standards/Approvals
JEDEC
Number of Cores
2
Automotive Standard
No
Country of Origin
Taiwan, Province Of China
Product Details
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
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€ 18.50
€ 18.50 Each (Exc. Vat)
€ 23.22
€ 23.22 Each (inc. VAT)
Stock information temporarily unavailable.
1
Technical Documents
Specifications
Brand
STMicroelectronicsProduct Type
Microprocessor
Series
STM32MP23xA/D
Device Core
ARM Cortex A35, ARM Cortex M33
Data Bus Width
16bit
Instruction Set Architecture
64 Bit, ARM V8-M, Arm Cortex
Maximum Clock Frequency
1.5GHz
Interface Type
SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet
Minimum Supply Voltage
1.71V
Package Type
TFBGA361
Maximum Supply Voltage
3.6V
Pin Count
361
Standards/Approvals
JEDEC
Number of Cores
2
Automotive Standard
No
Country of Origin
Taiwan, Province Of China
Product Details
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.